This invention relates to the field of binary counters, and more particularly to the field of synchronous programmable two-stage hybrid counters having a parallel part and a serial part for maximum speed and efficiency.
Synchronous parallel counters are fast, but require an increasing amount of gating logic for each additional stage. This makes them too expensive and inefficient for use in very long counters.
Linear feedback shift registers (LFSR) are very fast and efficient, but complex to program, since the sequence of numbers in the count is pseudo-random and programming of an LFSR requires an initialization value which must be looked up in a table as long as the maximum count of the LFSR or calculated by an algorithm which is non-trivial.
Very long counters have therefore frequently been implemented as ripple counters. However, ripple counters cannot easily produce a terminal count indication sychronously with the signal being counted.
What is desired is a binary counter that can be made very long, that can count fast, that is easily programmable, and that is capable of producing a terminal count indication that is synchronous with the signal being counted.